Plasma processing is widely used in the fabrication of semiconductor integrated circuits including some of the fundamental processes of plasma etching and deposition including plasma enhanced chemical vapor deposition (PECVD) and magnetron sputtering.
Vias are common structures used to vertically connect different metallization layers in integrated circuit. As illustrated in the cross-sectional view of FIG. 1, a lower dielectric layer 10 has a conductive feature 12 formed in its surface. An upper dielectric layer 14 is deposited over the lower dielectric layer 10 and its conductive feature 12 typically in a PECVD process. Photolithography including the patterning of a photoresist layer etches a via hole 16 through the upper dielectric layer 14 down to the conductive feature 12. The via hole 16 is filled with a metal to electrically connect the conductive feature 12 to another layer of metal formed above the upper dielectric layer 14. To prevent the metal from diffusing from the via 16 into the dielectric layer 14, a thin conformal barrier layer is deposited onto at least the sidewalls of the via hole 16 prior to the metal filling. Typical barrier materials are titanium for aluminum metallization and tantalum for copper metallization along with nitrides of the barrier metal. Magnetron sputtering is often used for depositing both the barrier metal and its nitride. This process for forming vertical interconnects may be repeated several times for the increasing number of metallization layers required for advanced logic circuits. In the lowest metallization level, the via is properly called a contact. In this case, a silicon layer replaces the lower dielectric layer 10 and the conductive feature may be a doped region in the silicon layer with accompanying contact layers such as silicides.
Many advanced integrated circuits replace the simple illustrated via with a dual-damascene structure having a narrow via formed in the lower portion of the dielectric layer and a connecting wider trench formed in the upper portion. The trench may extend axially over significant distances to provide horizontal interconnects in conjunction with the vertical interconnect of the via. The via and trench usually require separate etching steps but a single barrier deposition step and a single metal fill step are performed. The dual-damascene structure is particularly advantageous for copper metallization since copper is not readily etched. Instead, electrochemical plating (ECP) or related plating process fills the via and trench with copper and forms copper above the dielectric layer 14. Chemical mechanical polishing (CMP) removes the excess copper outside of the trench. The copper-filled trench may act as the conductive feature 12 in the lower metallization layer. Plating copper, however, requires a thin copper seed layer between the barrier layer to nucleate the copper formation and providing a plating electrode. Magnetron sputtering is most commonly used for depositing the copper seed layer. Further discussions of the via structure will apply equally well to dual-damascene structures, which often co-exist on the same chip.
In addition to the principal fabrication steps, plasma processing is also used for plasma treating pre-existing layers other than removing exposed layers as is done in etching. Plasma ashing performed after an etching process removes the patterned photoresist, typically composed of a carbonaceous polymer. Often prior to a deposition step, plasma pre-cleaning removes photoresist residues 18 and other contaminants settling on the via sidewalls wafer either because of prior processing or while the wafer is removed from the high-vacuum processing environment. Plasma pre-cleaning may also remove a native oxide layer 20 that has developed on exposed metal layers. Surface residues 22 may also form above the lip of the via hole.
Plasma treatments have recently been beneficially applied to low-k dielectric materials used to as the inter-level dielectric layer 14 in order to reduce capacitive coupling between narrowly spaced features and layers. Advanced low-k dielectrics having dielectric constants of 3 and below may have a significant carbon content and may also be porous to further decrease the dielectric constant. When vias are etched through dielectric layer to provide for vertical interconnects, the plasma etching may damage the soft low-k dielectric material. Further, the porous dielectric material may be unsatisfactory as a base for depositing subsequent barrier and metal layers. Accordingly, the practice has developed of both plasma cleaning the damaged low-k dielectric and of stuffing oxygen into the pores of the etched low-k material prior to the next deposition.